This invention relates to a semiconductor integrated circuit device (hereinafter termed a LSI) of the master slice type and more particularly a LSI wherein a region contained in the LSI exclusively used as a memory circuit is suitable for use as a register.
The master array system, also called a gate array, is usually prepared by forming on a semiconductor wafer a master chip in which a plurality of fundamental cells including a plurality of elements (including active elements such as transistors and passive elements such as resistors or the like) are integrated, coupling the elements in the fundamental cell to construct a logic circuit having desired logic performances and then connecting a plurality of such logic circuits to form a desired LSI.
FIG. 1 shows a conventional circuit construction of a cell contained in a gate array chip prepared in this manner and used exclusively as a memory circuit.
In this circuit, inverters 10 and 11 have the same size and the same electric characteristics and are connected in parallel opposition to form a flip-flop circuit. Gate circuits 12 and 13 are provided to act as transfer gate circuits to connect the flip-flop circuit to bit wires 14 and 15 respectively at the time of reading and writing data. The gate circuits 12 and 13 are enabled and disenabled by access signals for a memory circuit which are supplied to a word line 16 from an address decoder, not shown. The circuit is further provided with write drivers 17 and 18 which output data to be written onto the bit wires 14 and 15 at the time of writing data, and a sense amplifier 19 which shapes and amplifies the waveform of a slight voltage variation of bit lines 14 and 15 to obtain a voltage sufficient for reading.
A memory circuit having a construction described above is suitable for use as a memory circuit of a large capacity because it is possible to make small the memory cell area, but has the following disadvantage for use as a memory circuit contained in a gate array.
More particularly, in the gate array, in most cases, the memory circuit is utilized as a register group so that the memory circuit is required to effectively function as the register group. However, in the memory circuit described above, only one of reading and writing of data is possible so that such memory circuit is not effective as the memory group. This will be described with reference to FIG. 2.
In FIG. 2, 20 designates a register group utilizing the memory cell shown in FIG. 1 which comprises three addresses, A, B and C. 21 and 23 respectively designates single registers and 22 an arithmetic operation circuit executing a calculation Z.
Where the memory circuit is used as registers it is a usual practice to subject the content of the address A of the register group 20 and the content of the address B to an arithmetic operation Z and to store the result of the arithmetic operation in the address C. With the prior art memory circuit shown in FIG. 1, whether the data is read out or written, only one access can be made during one clock so that in order to use the memory circuit as registers, the following three step operations are necessary.
1. Read out the content of address A of the register group 20 and store the read out content in the other register 21 (the content thereof being designated by R1.) EQU (R1).rarw.(content of address A)
2. Read out the content of address B of the register group 20 and subject the read out content and the content (R1) of the register 21 to arithmetic operation Z of the arithmetic operation circuit 22 and store the result of calculation in other register 23 (the content thereof being designaged by R2), then, EQU (R2).rarw.(R1) .circle.Z (content of address B)
3. Read out the content (R2) of the register 23 and write the read out content in address C of register group 20, thus EQU (Content of address C).rarw.(R2)
As above described, where the prior art memory circuit is used as a register group, a general processing described above (a method of processing now being used generally) requires a processing time corresponding to 3 clocks. This means that the construction described above prevents improvements of the processing ability of the LSI as a whole.
Furthermore, the prior art memory circuit shown in FIG. 1 has the following disadvantages.
More particularly, a logic circuit utilizing a gate array is generally designed by a user not having a sufficient knowledge about semiconductor devices to realize that it is desired that various component elements constituting the gate array should have suitable operating margins for facilitating timing control or the like, since the operation of the memory circuit described above is complicated and difficult to effect proper timing control. Moreover, since the prior art memory circuit includes a sense amplifier 19 having a small operating margin, it is very difficult for the user to design the logic circuit.